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6.884 Complex Digital Systems, Spring 2005

NAND gate layout.

NAND gate layout from Lecture 3: CMOS Technology and Logic Gates. (Image by Professors Arvind and Asanovic.)

Highlights of this Course

This course features a complete set of lecture notes. In addition, labs are also available.

Course Description

This course is offered to graduates and is a project-oriented course to teach new methodologies for designing multi-million-gate CMOS VLSI chips using high-level synthesis tools in conjunction with standard commercial EDA tools. The emphasis is on modular and robust designs, reusable modules, correctness by construction, architectural exploration, and meeting the area, timing, and power constraints within standard cell and FPGA frameworks.
 

Staff

Instructors:
Prof. Arvind
Prof. Krste Asanovic

Contributor:
Prof. Chris Terman

Course Meeting Times

Lectures:
Three sessions / week
1.5 hours / session

Level

Graduate

Additional Features

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